An Exact Hardware Implementation of the Boltzmann Machine

We present a fast implementation of the Boltzmann Machine based on specialized hardware. This realization faithfully implements the machine; in particular, it avoids the excess parallelism which makes other fast implementations of it only approximate. The current prototype performs 505 million additions and multiplications (or megasynapses) per second. It can emulate the fully connected Boltzmann Machine with up to 1438 variables. Boltzmann Machine’s weights are expressed as 16-bit two’s complement fixed-point numbers. Our implementation is built on the top of DECperle-1, a reconfigurable coprocessor board based on field programmable gate arrays (FPGAs). DECperle-1 is closely coupled with its host processor (an ordinary workstation). In our application, it only performs the simplest and most computing-intensive part of the Boltzmann Machine algorithm, namely multiplying matrices of numbers by vectors of bits. The other operations (which are complicated, but only require a modest amount of computation) are performed by the host processor. This organization allows the specialized hardware to remain simple. Developing hardware algorithms for DECperle-1 is much easier and cheaper than building specialized hardware by traditional methods. This allowed us to experiment with several successive Boltzmann Machine implementations. The first version of the realization described here has been developed from scratch and fully tested by one person in less than a month.